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H.264/AVC is the latest international video coding standard, which provides a compression efficiency of up to 50% over a wide range of bit rates and video resolutions compared to previous standards. However, due to its high complexity, a full-software H.264/AVC codec possibly consumes all the resources of an embedded processor. This reduces its attractiveness or even makes it impractical for embedded applications. Therefore, a H.264/AVC codec implemented partially or fully in hardware would definitely be a more practical solution.

H.264 decoder block diagram
Features
Compliance with ITU-T H.264 Specification
Baseline and Main Profile Support
Real-time decoding at High Bitrates in FPGAs
Fully Synchronous Design
Interfaces to 32-bit RAM for Reference Frames
Single Core Configuration for QCIF up to HDTV @ 30 fps